why is the number of gate inputs to CMOS gates usually limited to four?
No Answer is Posted For this Question
Be the First to Post Answer
What are the different design techniques required to create a layout for digital circuits?
Advantages and disadvantages of Mealy and Moore?
What is LVS, DRC?
What are the different design constraints occur in the synthesis phase?
How to find the read failiure probablity in SRAM?
What is the ideal input and output resistance of a current source?
Describe the various effects of scaling?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What is the difference between fifo and the memory?
6 Answers DewSoft, Intel, Pentagon Rugged Systems,
How to improve these parameters? (Cascode topology, use long channel transistors)
What?s the critical path in a SRAM?
2 Answers Infosys, Intel, Texas,