What are the different design constraints occur in the synthesis phase?


No Answer is Posted For this Question
Be the First to Post Answer

Post New Answer

More VLSI Interview Questions

What does the above code synthesize to?

0 Answers   Intel,


Differences between IRSIM and SPICE?

0 Answers   Intel,


What are the different types of skews used in vlsi?

1 Answers  


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,


Cross section of an NMOS transistor?

3 Answers   Intel,






If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,


How do you detect if two 8-bit signals are same?

6 Answers  


what is multiplexer?

0 Answers  


Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,


Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,


For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 Answers  


What's the price in 1K quantity?

0 Answers   Wipro,


Categories