Answer / amruthaa b

The absolute delay is given by

Dabs = d.t where d is the delay of gate and t is the delay of inverter given by t = RC.

Insights of a 4bit adder/Sub Circuit?

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

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what is Channel length modulation?

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Implement F= not (AB+CD) using CMOS gates?

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

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What?s the difference between Testing & Verification?

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