Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

---

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

what is short Channel effect.

2 Answers  

---

What is the function of tie-high and tie-low cells?

0 Answers  

---

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

---

What is the ideal input and output resistance of a current source?

0 Answers  

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

---

Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

---

Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

---

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

---

What is polymorphism? (C++)

2 Answers   Intel,

---

Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

---