Give the various techniques you know to minimize power consumption?

5 Answers  

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What products have you designed which have entered high volume production?

0 Answers   Intel,

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Are you familiar with the term snooping?

1 Answers   Intel,

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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Draw the Layout of an Inverter?

0 Answers   Intel,

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What are the different gates where boolean logic are applicable?

0 Answers  

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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