Interested to Buy Any Domain ? << Click Here >> for more details...
What are the limitations in increasing the power supply to
reduce delay?
- 2 Answers
- 13460 Views
- Infosys, I also Faced
- E-Mail Answers
Answer Posted / arpan
increasing vdd increeases power dissipation as
switching power = c vdd**2 f
also at submicron level , increasing vdd amy lead to hgh
feild in the device....leading to its failure
| Is This Answer Correct ? | 10 Yes | 0 No |
Post New Answer View All Answers
What is Noise Margin? Explain the procedure to determine Noise Margin?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
What are the different ways in which antenna violation can be prevented?
What are the Factors affecting Power Consumption on a chip?
Draw the SRAM Write Circuitry
Insights of a 4bit adder/Sub Circuit?
Write a VLSI program that implements a toll booth controller?
Explain Basic Stuff related to Perl?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Explain Cross section of a PMOS transistor?
Explain how Verilog is different to normal programming language?
Why does the present vlsi circuits use mosfets instead of bjts?
What is the function of tie-high and tie-low cells?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
