Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What are the limitations in increasing the power supply to
reduce delay?

Answer Posted / narasimha reddy d l

power supply is directly praportional to the sub-micron
leakage current so if Vdd increases the leakage current
will increases

Is This Answer Correct ?    1 Yes 2 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

1278


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1301


Give various factors on which threshold voltage depends.

1309


Explain Basic Stuff related to Perl?

1052


why is the number of gate inputs to CMOS gates usually limited to four?

1348


Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1084


How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1211


what is multiplexer?

1170


What are the changes that are provided to meet design power targets?

1122


Mention what are the different gates where Boolean logic are applicable?

1134


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3871


Explain what is scr (silicon controlled rectifier)?

1065


what is SCR (Silicon Controlled Rectifier)?

1048


For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1281


Basic Stuff related to Perl?

2828