What are the limitations in increasing the power supply to
reduce delay?
Answer Posted / narasimha reddy d l
power supply is directly praportional to the sub-micron
leakage current so if Vdd increases the leakage current
will increases
| Is This Answer Correct ? | 1 Yes | 2 No |
Post New Answer View All Answers
What is the difference between cmos and bipolar technologies?
Insights of a 4bit adder/Sub Circuit?
what are three regions of operation of MOSFET and how are they used?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Basic Stuff related to Perl?
what is a sequential circuit?
How to improve these parameters? (Cascode topology, use long channel transistors)
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
What are the different design constraints occur in the synthesis phase?
What are the different design techniques required to create a layout for digital circuits?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Why does the present vlsi circuits use mosfets instead of bjts?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)