Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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What is setup time and hold time?

1 Answers   Intel,

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

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Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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What is pipelining and how can we increase throughput using pipelining?

1 Answers   Intel,

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6-T XOR gate?

0 Answers   Intel,

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Explain the Charge Sharing problem while sampling data from a Bus?

1 Answers  

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Implement F = AB+C using CMOS gates?

2 Answers   Intel,

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