Draw a transistor level two input NAND gate. Explain its sizing (a) considering

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

Question Posted / keerthireddy

No Answer is Posted For this Question
Be the First to Post Answer

More VLSI Interview Questions

Explain about 6-T XOR gate?

Insights of a 2 input NAND gate. Explain the working?

What is Noise Margin? Explain the procedure to determine Noise Margin?

Differences between IRSIM and SPICE?

What happens if we increase the number of contacts or via from one metal layer to the next?

Insights of a pass gate. Explain the working?

6-T XOR gate?

For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

Explain Custom Design Flow?

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

Have you studied buses? What types?

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

For more VLSI Interview Questions Click Here