Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

0 Answers   Intel,

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Basic Stuff related to Perl?

0 Answers   Intel,

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Explain what is scr (silicon controlled rectifier)?

0 Answers  

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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What types of CMOS memories have you designed? What were their size? Speed?

0 Answers   e-tec, Intel,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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