What is the ideal input and output resistance of a current source?

0 Answers  

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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What was your role in the silicon evaluation/product ramp? What tools did you use?

0 Answers   Intel,

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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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6-T XOR gate?

0 Answers   Intel,

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What is validation?

2 Answers   Intel,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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