VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

What happens to delay if we include a resistance at the output of a CMOS circuit?

Infosys,

1 13422

Give the expression for calculating Delay in CMOS circuit?

Infosys,

1 7508

what is charge sharing?

Intel,

2306

Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

Infosys,

2 16055

Explain the working of differential sense amplifier?

1 6438

What happens if we use an Inverter instead of the Differential Sense Amplifier?

Infosys,

3263

What?s the critical path in a SRAM?

Infosys, Intel, Texas,

2 11502

What happens if we delay the enabling of Clock signal?

2299

What?s the difference between Testing & Verification?

Infosys,

6 30273

How can you model a SRAM at RTL Level?

Infosys,

5683

what is Latch up?How to avoid Latch up?

3 24534

What happens if we delay the enabling of Clock signal?

4 7069

Explain the Charge Sharing problem while sampling data from a Bus?

4657

Explain why & how a MOSFET works?

Infosys,

2 6963

Explain the various MOSFET Capacitances & their significance?

1 23308

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Un-Answered Questions { VLSI }

Working of a 2-stage OPAMP?

3120

what is multiplexer?

1097

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1243

what is SCR (Silicon Controlled Rectifier)?

999

How binary number can give a signal or convert into a digital signal?

1135

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

1206

Explain the Working of a 2-stage OPAMP?

1143

What is Noise Margin? Explain the procedure to determine Noise Margin?

2412

What types of CMOS memories have you designed? What were their size? Speed?

3091

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3820

What is the main function of metastability in vsdl?

1005

What are the ways to Optimize the Performance of a Difference Amplifier?

2387

Explain what is Verilog?

1050

What is the difference between the mealy and moore state machine?

1035

What types of high speed CMOS circuits have you designed?

2510

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