Cross section of a PMOS transistor?
What are the steps involved in designing an optimal pad ring?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What is threshold voltage?
what is SCR (Silicon Controlled Rectifier)?
Why does the present vlsi circuits use mosfets instead of bjts?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
6-T XOR gate?
What are the different gates where boolean logic are applicable?
Explain the working of 4-bit Up/down Counter?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
What was your role in the silicon evaluation/product ramp? What tools did you use?
How does a Bandgap Voltage reference work?