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VLSI Interview Questions
Questions Answers Views Company eMail

What happens to delay if we include a resistance at the output of a CMOS circuit?

Infosys,

1 12552

Give the expression for calculating Delay in CMOS circuit?

Infosys,

1 6743

what is charge sharing?

Intel,

1892

Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

Infosys,

2 14878

Explain the working of differential sense amplifier?

 1 5766

What happens if we use an Inverter instead of the Differential Sense Amplifier?

Infosys,

2732

What?s the critical path in a SRAM?

Infosys, Intel, Texas,

2 10252

What happens if we delay the enabling of Clock signal?

 1810

What?s the difference between Testing & Verification?

Infosys,

6 27981

How can you model a SRAM at RTL Level?

Infosys,

5261

what is Latch up?How to avoid Latch up?

 3 23155

What happens if we delay the enabling of Clock signal?

 4 5791

Explain the Charge Sharing problem while sampling data from a Bus?

 4180

Explain why & how a MOSFET works?

Infosys,

2 5928

Explain the various MOSFET Capacitances & their significance?

 1 22455

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Un-Answered Questions { VLSI }

Are you familiar with the term snooping?

2925

Explain depletion region.

619

Explain the operation considering a two processor computer system with a cache for each processor.

2352

Explain what is the use of defpararm?

659

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1789




What transistor level design tools are you proficient with? What types of designs were they used on?

4571

Draw the Layout of an Inverter?

2049

Explain what is Verilog?

639

Explain how logical gates are controlled by Boolean logic?

630

What is the ideal input and output resistance of a current source?

2517

How does a Bandgap Voltage reference work?

3250

What is the function of enhancement mode transistor?

636

What is the purpose of having depletion mode device?

621

What are the different classification of the timing control?

580

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

714

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