Answer / arun

critical path occurs during reading operation
so ready delay = precharge delay + row deocder delay+
bitline discharge delay+ sense amplifier delay+ mux delay

Answer / mayank jansari

critical path is longest costing path in SRAM

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

---

Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

---

Cross section of an NMOS transistor?

3 Answers   Intel,

---

What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

---

---

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

0 Answers   Infosys,

---

Insights of a Tri-state inverter?

1 Answers   Intel,

---

Why do we use a Clock tree?

3 Answers   Intel,

---

Explain why & how a MOSFET works?

2 Answers   Infosys,

---

Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

---

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,

---