How does Resistance of the metal lines vary with increasing thickness and increasing length?
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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
what is the use of defpararm?
Explain the working of 4-bit Up/down Counter?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
What are the main issues associated with multiprocessor caches and how might you solve them?
What types of high speed CMOS circuits have you designed?
Are you familiar with the term snooping?
What happens if we delay the enabling of Clock signal?
How to improve these parameters? (Cascode topology, use long channel transistors)
Explain depletion region.
Explain CMOS Inverter transfer characteristics?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
What is the difference between synchronous and asynchronous reset?
What was your role in the silicon evaluation/product ramp? What tools did you use?
