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How does Resistance of the metal lines vary with increasing thickness and increasing length?
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Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Working of a 2-stage OPAMP?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is the function of tie-high and tie-low cells?
What are the different design constraints occur in the synthesis phase?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Explain the Charge Sharing problem while sampling data from a Bus?
What are the ways to Optimize the Performance of a Difference Amplifier?
Explain Cross section of an NMOS transistor?
Implement a 2 I/P and gate using Tran gates?
Explain how logical gates are controlled by Boolean logic?
How to improve these parameters? (Cascode topology, use long channel transistors)
Write a VLSI program that implements a toll booth controller?
What are the different design techniques required to create a layout for digital circuits?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
