Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What is SPICE?

4 Answers   Intel,

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Explain the usage of the shared SPI bus?

1 Answers  

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What is look up table in vlsi?

0 Answers  

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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