Give the cross-sectional diagram of the cmos.

0 Answers  

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what is verilog?

0 Answers  

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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What happens if we delay the enabling of Clock signal?

0 Answers  

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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