How binary number can give a signal or convert into a digital signal?

0 Answers  

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What happens to delay if you increase load capacitance?

3 Answers   Infosys,

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Draw the Layout of an Inverter?

0 Answers   Intel,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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Tell me how MOSFET works.

0 Answers  

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How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

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what is multiplexer?

0 Answers  

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