Answer / musammil.k

when balanced condition load,the phase current is passing through among phases(RYB).

There are 2 Flip_Flop with logic between them. Given Clock to Q delay, logic prop. delay, set up and hold times specify maximum clock frequency of system. What happens if second output fed back to first input. Any changes? What happens with timing if second output is fed back to logic between the flops? Good Luck!

1 Answers   Qualcomm,

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Draw a SLD of HT distribution EB grid up to users Transformer?

0 Answers   HSL, VVL,

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we use capister for power factor. when we use capaciter in dg circuit  than defect dg. can we use capaciter bank for dg circuit

0 Answers   Syncom,

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what is corona effect

3 Answers  

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What is the power ratio between power in Star and Delta circuit?

3 Answers  

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what is the requirement of commutator in a universal motor?

3 Answers  

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what happens if commutator is removed in an dc machine?

3 Answers  

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How can we convert 11 kv to 440 volt without using transformer ?

0 Answers   Electrical,

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Dear Mr B C pal...Can you plz. put some light on principle of operation of Z-Ct in conjunction to its use with 1Cx1000Sqmm HT Cables & Directional Ground Fault / Over Voltage Relays...Regd..Parag v K 9899115632

0 Answers  

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If you don’t have coal, salt and copper, then how would you earth your connection temporarily at a campus site?

2 Answers  

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How to Calculate The sag of OPGW in Transmission Line???

0 Answers   Zenco Systems,

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What are the various methods for effecive earthing in a factory in a rocky terrain, where soil resistivity is extraordinarily high? The usual method of 3 m deep earth pits is not serving the purpose.

4 Answers  

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