Answer Posted / pankaj

power is dirlectly proportional to the square of suplly
voltage so is the supply voltage reduces the power is also
reduced but the lekage cuurent is increased. so voltage
level can't be reduced so much.

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1457

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Explain what is the depletion region?

1087

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What is the difference between the mealy and moore state machine?

1119

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What happens if we delay the enabling of Clock signal?

2372

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3867

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Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1110

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1605

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Working of a 2-stage OPAMP?

3186

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Basic Stuff related to Perl?

2819

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For CMOS logic, give the various techniques you know to minimize power consumption

1410

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Draw a CMOS Inverter. Explain its transfer characteristics

1185

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1203

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Design an 8 is to 3 encoder using 4 is to encoder?

1331

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Mention what are the two types of procedural blocks in Verilog?

1303

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What is threshold voltage?

1186

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