Answer Posted / srujana

Power consumption on a chip can be classified majorly in
to 2 types:
1. Static Power consumption
2. Dynamic Power consumption
Static Power consumption: Leakage power is the major
contributor in static power consumption. The subthreshold
leakage power due to reduced threshold value due to
reduced supply voltages as technology is shrinking is the
major contributor of leakage power.
Dynamic Power consumption:
1.This is due to the increase in frequency of the chip,
which results in high switching rates of the clock
2. Due to increase in the complexity of the chip and the
increase in the instance count of the chip.

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973

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1228

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1030

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1184

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1089

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1007

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1234

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1059

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1234

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2813

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1022

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996

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For CMOS logic, give the various techniques you know to minimize power consumption

1349

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2626

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1194

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