Factors affecting Power Consumption on a chip?
- 7 Answers
- 14802 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / bhawna
In addition to Static and Dynamic Power the other major contributor is:
Activity factor - how often the gates are switching
Optimal sizing - same logical effort is approximately same delay however the least size will give least power
Total Capacitance charging/discharging per cycle - depends on optimal layout design to reduce the capacitance by proper choice of available metal layers
| Is This Answer Correct ? | 2 Yes | 0 No |
Post New Answer View All Answers
Explain sizing of the inverter?
Explain the three regions of operation of a mosfet.
Cross section of a PMOS transistor?
Design an 8 is to 3 encoder using 4 is to encoder?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
what is a sequential circuit?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is the function of tie-high and tie-low cells?
Differences between Array and Booth Multipliers?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
What is Noise Margin? Explain the procedure to determine Noise Margin?
Are you familiar with the term snooping?
Write a VLSI program that implements a toll booth controller?
