1,what is the different between signal and variables in VHDL? 2,what is the d

1,what is the different between signal and variables in
VHDL?
2,what is the different between function and procedure in
VHDL?

Question Posted / venkat stony

1 Answers
3415 Views
Bosch, I also Faced
E-Mail Answers

1,what is the different between signal and variables in VHDL? 2,what is the different between fun..

Answer / jimmy.gugon

Hello,
A function returns 1 value whereas a procedure can return
multiple values? Could someone elucidate this for me? Also, I
am confused about the scope of signals. If I declare a signal
within an architecture, does the scope of this signal extend
to functions declared within processes in the architecture? If
not, is there a way to do this without passing the signals? I
would like to call functions in a way resembling scripts that
allowed for greater code readability.

Is This Answer Correct ?

0 Yes

3 No

Post New Answer

More Electronics Communications Interview Questions

Define modulation.

0 Answers

plz send last 5 year paper set for JE-II(ELECTRICAL)Exam held on few month in mumbai

0 Answers RRB,

Explain GPRS architecture.

0 Answers BSNL,

What is meant by gain-bandwidth product? What is its significance?

0 Answers

how we will write a query for highest salary

1 Answers

What is the disadvantage of on-off control?

0 Answers

tell 10 points about indian education and foreign education?

0 Answers Accenture, CTS,

what is the importance of signals and systems ?

3 Answers ABC,

The function of a transistor used in any of the ics is to perform switching action and not amplification. Then why diodes are not used instead of transistors as diodes also exhibit the same switching action?

0 Answers

When two UPS are connected in parallel, can you have a bypass raw power supply connected across? Please explain

1 Answers

What is an amplifier?

0 Answers

what is practical application of clamper circuit?

1 Answers

For more Electronics Communications Interview Questions Click Here