1,what is the different between signal and variables in
VHDL?
2,what is the different between function and procedure in
VHDL?
Answer / jimmy.gugon
Hello,
A function returns 1 value whereas a procedure can return
multiple values? Could someone elucidate this for me? Also, I
am confused about the scope of signals. If I declare a signal
within an architecture, does the scope of this signal extend
to functions declared within processes in the architecture? If
not, is there a way to do this without passing the signals? I
would like to call functions in a way resembling scripts that
allowed for greater code readability.
| Is This Answer Correct ? | 0 Yes | 3 No |
Explain the importance of if in radio receiver?
Describe the purpose of knee point voltage for differential protection.
What is current commutation?
Charging & discharging of capacitor.
What is the use of induction motor?
why oscillators are used in micro controllers?
why do we use 4to20mA not a 0to20mA?
What are the main classification of inverter?
why rs232 is used in uart when there are many rs devices like rs449 etc . what is the main advantage in using rs232
The microcontroller perform one function at a time.whether it is advantage of microcontroller or disadvantage of microcontroller
Convert the 16 W power into dBm.
What do you mean by half-duplex and full-duplex communication? Explain briefly.
Civil Engineering (5086)
Mechanical Engineering (4456)
Electrical Engineering (16639)
Electronics Communications (3918)
Chemical Engineering (1095)
Aeronautical Engineering (239)
Bio Engineering (96)
Metallurgy (361)
Industrial Engineering (259)
Instrumentation (3014)
Automobile Engineering (332)
Mechatronics Engineering (97)
Marine Engineering (124)
Power Plant Engineering (172)
Textile Engineering (575)
Production Engineering (25)
Satellite Systems Engineering (106)
Engineering AllOther (1379)