Is there a possibility to use such a treshold voltage for the NMOS part of a CMOS circuit that during the switching it will start conducting only after the PMOS part will be already closed, by this eliminating the leakedge current? Please note, I'm not asking about the well bias in standby mode, but about the "antileakedge" measures during normal operation.

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IF 8255 CONTROL WORD IS 94H,Tell the chip port work mode ?

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difference between ordinary MCCB & Motorised MCCB

4 Answers  

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How does a VOLTAGE OPERATED DIFFERENTIAL RELAY work??

2 Answers  

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we the the value of frequency is 50 HZ in DG then why we said the value inductive rectance is zero in DG?

1 Answers  

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What is Traction? 1KVA Alternator, How much urrent taken?

0 Answers   Bhel,

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what will happen if OLR CT in all phases are short circuted

0 Answers   Indfrag Limited,

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what is the main function of capacitors in mccs.

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Transformer cores are laminated in order to A simplify its construction B minimize eddy current loss C reduce cost D reduce hysterisis loss

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-How do you select cable size for a given load at a given distance from source of supply. How do you find voltage drop.

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How Flywheel run in DG set, tell in details

1 Answers   Sambhav, TATA,

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What is the difference between single core 2 wire and single core 3 wire system? Which application we are using this? and for What purpose we are using this?

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