Answer / madhu

if we increase power supply to reduce delay ,delay will
reduces but power dissipation will be high and to
compensate the excessive power we have to increase die size
which is impractical.

Answer / bauer

There are also Mobility Degradation and Subthreshold Conduction which directly depend on the Voltage and Temperature.

Are you familiar with the term MESI?

1 Answers   Intel,

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Explain what is Verilog?

0 Answers  

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What is polymorphism? (C++)

2 Answers   Intel,

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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What are the steps involved in preventing the metastability?

0 Answers  

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Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

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What is the build-in potential?

1 Answers   Wipro,

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,

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Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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