What are the different limitations in increasing the power
supply to reduce delay?
- 2 Answers
- 7712 Views
- I also Faced
- E-Mail Answers
Answer Posted / madhu
if we increase power supply to reduce delay ,delay will
reduces but power dissipation will be high and to
compensate the excessive power we have to increase die size
which is impractical.
| Is This Answer Correct ? | 9 Yes | 0 No |
Post New Answer View All Answers
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
What are the steps required to solve setup and hold violations in vlsi?
What are the different gates where boolean logic are applicable?
Explain what is scr (silicon controlled rectifier)?
How does Vbe and Ic change with temperature?
How does a Bandgap Voltage reference work?
Give the cross-sectional diagram of the cmos.
How binary number can give a signal or convert into a digital signal?
What is Body Effect?
Explain the working of 4-bit Up/down Counter?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Cross section of a PMOS transistor?
What are the steps involved in designing an optimal pad ring?
How can you construct both PMOS and NMOS on a single substrate?
What is look up table in vlsi?
