Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

0 Answers   Infosys,

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What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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Explain how MOSFET works?

0 Answers  

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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What are the different gates where boolean logic are applicable?

0 Answers  

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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What are the different classification of the timing control?

0 Answers  

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What is component binding?

2 Answers   Intel,

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What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

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Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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Who provides the DRC rules?

5 Answers   Intel,

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