Is there a possibility to use such a treshold voltage for the NMOS part of a C

Is there a possibility to use such a treshold voltage for
the NMOS part of a CMOS circuit that during the switching
it will start conducting only after the PMOS part will be
already closed, by this eliminating the leakedge current?
Please note, I'm not asking about the well bias in standby
mode, but about the "antileakedge" measures during normal
operation.

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