What is the build-in potential?

1 Answers   Wipro,

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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What is Fermi level?

5 Answers  

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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Explain about 6-T XOR gate?

0 Answers   Intel,

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what is the difference between the testing and verification?

1 Answers   Intel,

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WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

5 Answers   Intel, Wipro,

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What is a linked list? Explain the 2 fields in a linked list?

1 Answers   Intel,

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