Answer Posted / sham
w r t VHDL component binding is binding of an entity with an architecture declared else where..
| Is This Answer Correct ? | 1 Yes | 0 No |
Post New Answer View All Answers
Draw the Layout of an Inverter?
What is the purpose of having depletion mode device?
Explain how binary number can give a signal or convert into a digital signal?
What is the function of enhancement mode transistor?
Differences between IRSIM and SPICE?
what is multiplexer?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Are you familiar with the term MESI?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Explain how MOSFET works?
What was your role in the silicon evaluation/product ramp? What tools did you use?
What does it mean “the channel is pinched off”?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Explain CMOS Inverter transfer characteristics?