Answer / pujitha

because fall time is less than rise time...so the input can
be applied faster to the circuit..delay is less

Answer / shubham

to maintain synchronisation... bec all the signals are taken as active during +ive level .. so to remove ambiguity we take -ive level as active for clock..

Answer / pathugovan

negative clock input means '0'.In this flip flop we give a input in negative it invert and finaly give positive output.that why we always give negative input.

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