Interested to Buy Any Domain ? << Click Here >> for more details...
why we most prefer negative clock input(negative level) most
in all flip flop answer
- 3 Answers
- 5254 Views
- I also Faced
- E-Mail Answers
Answer Posted / pujitha
because fall time is less than rise time...so the input can
be applied faster to the circuit..delay is less
| Is This Answer Correct ? | 3 Yes | 1 No |
Post New Answer View All Answers
i need modal Q. paper of junior enjineer for 1/2009 rrb ajmer exam cat no. 11 jell electrical thenkyou
Discuss the need for biasing the transistor.
how to write test cases?
how to answer for the question what is your strength and weakness?
What are the maintenances of SCADA ?
Explain what is an inverting amplifier?
Fr aptitude question which for preparing good book?
How the trx is assigned to e1 channel?
Plz send me some sample papers on OCES papers. I am appearing in OCES/DGFS-2009.Plz inform me by my emailid- subhabrata03851@gmail.com
What is the effect of removal of bypass capacitor in a ce amplifier circuit?
give some important questions in Airport Authority of india junior Engineer ATC exam?
What is a mosfet? How is it different from a jfet? What are its typical applications?
What is firing angle?
what type of quesions asks in interview?
For a 1φ voltage controller, feeding a resistive load, draw the waveforms of source voltage, gating signals, output voltage and voltage across the scr. Describe the working with reference to waveforms drawn?
