86 Family (470)
VLSI (297)
DSP (55)
Embedded Systems AllOther (399) If a1M1× DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.
CDAC,
1258In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing
CDAC,
1495What number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00hA1: INC AL JNZ A1
CDAC,
1413
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Given time, cost, client satisfaction and best practices, how will you prioritize them for a project you are working on? Explain why.
What type of architecture is used in 8085 microprocessor?
In how many groups can the signals of 8085 be classified?
What is an interrupt? List various types of interrupts available in 8051 microcontroller?
How about voltage source?
What are the advantages of memory segmentation in 8086
Explain various adders and difference between them?
What is the function of enhancement mode transistor?
What is the bus arbitration problem in the 8086 and how can it be resolved?
what are the differences between isolated i/o and memory mapped i/o
What are the software instructions related to stack operations?
What is risc architecture?
Do the interrupts of 8085 have priority?
Describe the instruction register of 8085?