If a1M1× DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.
CDAC,
782In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing
CDAC,
1003What number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00hA1: INC AL JNZ A1
CDAC,
960
Tell me whether we can use semaphore or mutex or spinlock in interrupt context in linux kernel?
Explain what type of architecture is used in 8085 microprocessor?
Define the process of an interrupt operation in the 8086?
How many i/o ports can 8085 access?
Differentiate testing and verification?
Describe the various effects of scaling?
What does the eu do in the 8086?
Tell me can a pointer be volatile?
When is the LOCK prefix used often?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
With the help of an example explain how physical address is calculated?
Explain how does combination of functions reduce memory requirements in embedded systems?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
What are issues related to stack and bank 1.?
What is watchdog timer?