86 Family (470)
VLSI (297)
DSP (55)
Embedded Systems AllOther (399) If a1M1× DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.
CDAC,
1265In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing
CDAC,
1498What number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00hA1: INC AL JNZ A1
CDAC,
1417
Which is the best way to write loops?
What is the function of dma controlled in embedded system?
Can an rc circuit be used as clock source for 8085?
Explain me what is the main function of multiplexed address/data bus?
What are the temporary registers of 8085?
Which interrupt has highest priority?
What are the different types of instructions responsible for data transfer instructions.
What is special purpose registers in 8086?
What are hard and soft real time systems?
How does combination of functions reduce memory requirements in embedded systems?
What is the use of microprocessors?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Design a transmission gate based xor.
What is yagni? Is this list of questions an example?
What is priority inheritance?