Answer / sivakumar

we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.

Answer / ekta

we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.

Answer / shinz

in a level triggered JK flipflop, if J=K=1 and if the pulse width of the clock is very much greater than propagation delay, then the output will toggle more than one time.this condition is known as race around condition

Answer / shikha chauhan

The condition S=R=1 is not allowed in SR flip-flop, this is
eliminated by JK flip flop by using feedback connection
from output to input of gate 1 and 2 because of the
feedback connection Q(Q')at the i/p to K(J). The i/p will
change during clk pulse CP=1, if the o/p changes the state.

Answer / jenson

in a race around condition the output depends onthe
relative operating speed of 2 or more components.

Answer / yogesh

in jk flip flop race around problem will accur when both
the inputs are high.
it can be prevented by using
master slave jk flip flop.

Answer / manilal

O\P change more than once 4 specfc i\p then it is said to be race around condition .j=1,k=1 ,nd clok-1 o\p togles or flipflop wil confusing whch flipflop wil enable or not so flip flop race around or competitive against one another that is due to o\p togles depndng up on prevous state

Answer / praveen kishor

Drawback in jk flip flop is Race arround condition which is eliminated in D flip flop is called Race arround condition.

Answer / bineesh p babu

In J-K Flip flop, The clock time is higher than the output toggling time then for J=1 & K=1 , the output will be changed irrelevant of our input. This condition is known as Race around condition.

Answer / neha

when both the inputs are in low condition in JK flip this condition is called race around condition

What are the two types of cyclo-converters?

0 Answers  

hi.i want to get cleared about ece and want to know what are the topics or chapters which were in 11 and 12 grade.esp., in maths and physics?ans me soon.i am fresher.

0 Answers  

explain 8085 and 8086

3 Answers   Tech Mahindra,

What is the difference between Synthesised Frequency Hopping and Base Band Frequency Hopping?

0 Answers  

What do you mean by vision and mission?

0 Answers  

What are the specifications of the scr ?

0 Answers  

Explain how does a signal differ from a wave?

0 Answers  

What are the advantages and disadvantages of quine-mc cluskey method?

0 Answers  

What are electronic devices and components?

0 Answers  

please guide me who to prepare for bel interview...

0 Answers  

What is graticule?

0 Answers  

at the time of doing second year which course can we study..? and where we should study...?

0 Answers