Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 Answers  

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Basic Stuff related to Perl?

0 Answers   Intel,

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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Explain Custom Design Flow?

2 Answers   Intel,

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Are you familiar with the term MESI?

1 Answers   Intel,

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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What is validation?

2 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

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