Answer / Omendra Singh

Edge-triggered flip-flops (D type or JK type) change their output states at the transition of the clock pulse, either rising edge (positive-edge triggering) or falling edge (negative-edge triggering). Level-triggered flip-flops (SR type), on the other hand, change their output states based on the level of the clock signal. This means that the clock pulses are sampled during the stable periods of the clock cycle.

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