What is FPGA?

7 Answers   Intel,

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Explain how Verilog is different to normal programming language?

0 Answers  

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Explain the sizing of the inverter?

1 Answers   Intel,

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what is short Channel effect.

2 Answers  

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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Explain Custom Design Flow?

2 Answers   Intel,

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Cross section of a PMOS transistor?

0 Answers   Intel,

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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