In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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Define threshold voltage?

32 Answers   College School Exams Tests, Intel, JHG, Wipro,

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Explain what is the depletion region?

0 Answers  

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Explain the difference between write through and write back cache.

2 Answers   Intel,

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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Explain various adders and difference between them?

0 Answers   Intel,

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what is Latch up?How to avoid Latch up?

3 Answers  

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,

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