Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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How do you detect if two 8-bit signals are same?

6 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

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What is the main function of metastability in vsdl?

0 Answers  

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What is charge sharing?

2 Answers   Cypress Semiconductor, Intel,

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Explain the working of Insights of a pass gate ?

0 Answers   Intel,

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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Insights of a Tri-state inverter?

1 Answers   Intel,

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How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,

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