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Convergys Interview Questions
Questions Answers Views Company eMail

Tell me about yourself?

229 488257

I have done B.Sc.(H)Zoology).I went for an interview in a call centre.Cleared seven rounds there.Only I was selected out of 50 people for HR round.In HR round the HR manager asked me "Why you want to join a call centre after doing B.Sc.?" I couldn't answer and lost the interview.

11 28594

I have to give interviews in various airlines for cabin Crew.So,plz tell me abt various ques. Which r expected by Them

6 29209

How does QTP identifies the object in the application

6 20820

why do you think that i have to recuit you?

8 18829

where do you see yourself from (Ten or fifteen)years from now?

16 86405

Why do you want to work for this organization?

2 16918

How long would you expect to work for us if hired?

8 24960

why bpo

22 136618

Convergys Placement Paper - 08 nov 2006

4 13133

Define MultiOrg Structure

5 11951

Is SOB is attached with Business grp ?

2 15847

How will U link GL with OU in Multi-org environment.

3 8722

diff between key and descriptive flexfield.

4 8700

What are the tables in GL?

3 17487

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Un-Answered Questions

What is waiting time and Response time in windows operating system?

5


How idoc is posted to r/3 system?

522


What are all the operating system that python can run on?

464


What is the differences between static and dynamic drilldowns?

501


What are the logging in and out commands in aix?

3






what is settlement profile...when i m doing varient configuration i am facing this problem while creating sales order plz explain me......

2899


What are the different components of rails ?

491


what are the significances of maxwell's thermodynamic equations.

1638


What is the use of document and rendrer in lightning component? : salesforce lightning component

181


What are the problems associated with using javascript, and are there javascript techniques that you discourage?

594


What is the default operating system of raspberry pi, may I use any other operating systems?

1


How to edit a spreadsheet in excel?

274


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

4727


what is transistors comprised of?

645


Can you discuss the role of genetic testing in identifying hereditary neuromuscular diseases?

1