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Covansys Manual Testing Interview Questions
Questions Answers Views Company eMail

In development costs what percent Software testing accounts?

3 13396

what type of documents can u prepare during Testing?

5 12613

What is the diffrence between product base company and application company ? if product base name few products,if service base name the few services.

4 6298

What are the activities involved by the Test engineer (having 2+ yrs of exp).

1 4076

What are the documents required to prepare test plan?

10 24488





What are the different types of models?

8 9736

What is the diff. Between Waterfall and Spiral model?

17 65024

What is testing life Cycle and Explain different phases?

3 11011

What is the difference between SRS and FS?

3 11939

What is the difference between Functional requirement and business requirements?

2 6924

Explain?V?model?

1 3660

What are the different roles of testers in Verification and Validation?

2 4496

What is a test requirement?

5 5869

How to derive test requirements from SRS?

3 5992

What are the different test techniques?

3 6196

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Un-Answered Questions

what is class module in vb6? what it's use? with example..

1155


what is the last major networking problem you trouble shoot and solved on your own in the last year?

564


list some common errors faced with jspm while updating java stcks.and solutions.

1389


How is Flume-NG different from Flume 0.9?

5


How do you execute the payroll

1238






Explain the Calculation of Sales Tax?

883


Can you send me advertisement format for lost of E-1 form. kindly do the needful urgently. Thanks AP

696


1.What is the difference between method validation and method verification 2.Which guidelines proposed to method transfer

212


i am working with OC 4.5 i have numbers in table in 10 row with some null values please tell me how to find total? Thanks

930


what is the difference between read the data from table and infotype

1317


Dear sir/madam, plz sand me techanical test question (mechanical)

762


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

3934


Write a program to sort the number with different sorts in one program ??

1160


What does mean by Scope of Automation?n How we defined it?

825


What is the SimpleTimeZone class?

968






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