Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

4 Answers  

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Explain the usage of the shared SPI bus?

1 Answers  

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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what is charge sharing?

0 Answers   Intel,

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What happens to delay if you increase load capacitance?

3 Answers   Infosys,

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What is Fermi level?

5 Answers  

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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