What is Noise Margin? Explain the procedure to determine
Noise Margin?

Answers were Sorted based on User's Feedback



What is Noise Margin? Explain the procedure to determine Noise Margin?..

Answer / pradeep

Noise margin simply means margin for noise. it can tolerate
some amount of noise. The senders must be held at higher
standards than the receivers. For a 5V level, a voltage
above 4.5V is considered 1, and for receiver the voltage
above 3.5V is considered 1. therefore, the noise margin
4.5-3.5=1V.
it is deigned by looking at voltage transfer function.

Is This Answer Correct ?    49 Yes 3 No

What is Noise Margin? Explain the procedure to determine Noise Margin?..

Answer / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

Is This Answer Correct ?    52 Yes 27 No

What is Noise Margin? Explain the procedure to determine Noise Margin?..

Answer / shubham sharma

"noise margine is the max. voltage that can be added to the
logic gate input which will not affect the output."
voh>vih>vil>vol

vil=0,vol=0.
vih=1,voh=1.

Is This Answer Correct ?    11 Yes 4 No

What is Noise Margin? Explain the procedure to determine Noise Margin?..

Answer / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

Is This Answer Correct ?    12 Yes 36 No

Post New Answer

More VLSI Interview Questions

Explain Cross section of an NMOS transistor?

0 Answers   Intel,


Are you familiar with the term snooping?

1 Answers   Intel,


Cross section of an NMOS transistor?

3 Answers   Intel,


In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,


what is Slack?

0 Answers  






Give the various techniques you know to minimize power consumption?

5 Answers  


Explain the sizing of the inverter?

1 Answers   Intel,


Mention what are three regions of operation of mosfet and how are they used?

0 Answers  


What happens to delay if you increase load capacitance?

1 Answers   Google,


What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,


Explain various adders and diff between them?

1 Answers   Intel,


In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,


Categories