Explain Cross section of an NMOS transistor?
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Id vs. Vds Characteristics of NMOS and PMOS transistors?
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What types of CMOS memories have you designed? What were their size? Speed?
Draw the stick diagram of a NOR gate. Optimize it
Explain the operation considering a two processor computer system with a cache for each processor.
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
Draw the SRAM Write Circuitry
What is Fowler-Nordheim Tunneling?
Tell me how BJT works.
What are the different ways in which antenna violation can be prevented?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?