Factors affecting Power Consumption on a chip?

7 Answers   Intel,

---

Explain the Charge Sharing problem while sampling data from a Bus?

0 Answers  

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

0 Answers   Infosys,

---

Give the expression for calculating Delay in CMOS circuit?

1 Answers   Infosys,

---

Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

---

---

A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

---

What products have you designed which have entered high volume production?

1 Answers   Intel,

---

What are set up time & hold time constraints? What do they signify?

3 Answers  

---

Differences between D-Latch and D flip-flop?

17 Answers   AIT, Intel, Sibridge Technologies,

---

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

---

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

---