Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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what is Early effects and their physical origin.

1 Answers  

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What is the difference between nmos and pmos technologies?

0 Answers  

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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Draw a CMOS Inverter. Explain its transfer characteristics

0 Answers   Infosys,

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Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

0 Answers   Intel,

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what is verilog?

0 Answers  

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

0 Answers   Infosys,

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What is Fowler-Nordheim Tunneling?

2 Answers   Intel,

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what is the difference between the testing and verification?

1 Answers   Intel,

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