Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
No Answer is Posted For this Question
Be the First to Post Answer
Explain Cross section of an NMOS transistor?
For CMOS logic, give the various techniques you know to minimize power consumption
Why does the present vlsi circuits use mosfets instead of bjts?
What are set up time & hold time constraints? What do they signify?
Describe the various effects of scaling?
What is FPGA?
what is the difference between the testing and verification?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
How binary number can give a signal or convert into a digital signal?
verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.
2 Answers Cosmic Circuits, HP,
For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?