Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

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Explain about 6-T XOR gate?

0 Answers   Intel,

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Explain the sizing of the inverter?

1 Answers   Intel,

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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What is SPICE?

4 Answers   Intel,

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