verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.
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Answer / arpan
1. NMOS passes good logic 0 and bad logic 1.
We know the current conduction takes place when the channel
is formed i.e when Vgs > Vt(Threshold voltage). In normal
operation suppose Vg = 5v and Vs = 0v and Vt = 1v.
Fot the above mentioned case Vgs=Vg-Vs
=5v which is
grater than threshold voltage and logic 0 will easily pass.
Now if we want to pass logic 1, we have to make Vs=Vdd
(Suppose 5v). In this case Vgs=0v which is less than
threshold voltage, thus channel is not formed. And a bad
logic 1 is passed.
2. PMOS passes good logic 1 and bad logic 0
For normal operation suppose Vg = 0v and Vs = 5v
and Vt= -1v(threshold voltage for PMOS is -ve). So, Vgs =
-5v. So gate yo source voltage is more -ve and thus channel
will easily form, and logic 1 is passed easily. Now, suppose
Vs= 0v then Vgs=0v. Which is not -ve compare to Vt of PMOS,
thus channel will not form and will pass bad logic 0.
Refer pg 66 of Weste Harris
| Is This Answer Correct ? | 67 Yes | 7 No |
Answer / chakrapani
if vgs made more means more electronics are attraced to the
channel region so pinch off occures at large valves of vds
| Is This Answer Correct ? | 3 Yes | 7 No |
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