Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


Advantages and disadvantages of Mealy and Moore?

Answers were Sorted based on User's Feedback



Advantages and disadvantages of Mealy and Moore?..

Answer / sudeep

Moore Model:-
1. Advantage of moore model is easy to code, it is
simplification of the design.
2. It leads to slower bcoz of clocking the output but leads
to stable ouput.
3. Moore will have more number of states compared to mealy.


Mealy Model:-
1. Mealy leads to reduction in number of states
2. Mealy is complicated compared Mooree.
3. Mealy is faster bcoz output will change as soon as input
changes, but it leads to asychronus outputs leading to
metastability.

Is This Answer Correct ?    55 Yes 15 No

Advantages and disadvantages of Mealy and Moore?..

Answer / akasaramanna

Mr.sudeep r u really knows the answer r not?
endibey badacow ne istamonchina answer isthava?
donganayala?proper ga answer thelistene pumpinchu lekapote
kinda,pina moosukoni kurcho.

Is This Answer Correct ?    16 Yes 31 No

Post New Answer

More VLSI Interview Questions

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,


Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,


Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,


In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,


How about voltage source?

0 Answers  


Explain what is the use of defpararm?

0 Answers  


A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,


What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,


What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,


Mention what are the different gates where Boolean logic are applicable?

0 Answers  


What are the different gates where boolean logic are applicable?

0 Answers  


Categories