Describe the various effects of scaling?

0 Answers   Infosys,

---

What's the price in 1K quantity?

0 Answers   Wipro,

---

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

---

What are the changes that are provided to meet design power targets?

0 Answers  

---

6-T XOR gate?

0 Answers   Intel,

---

Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

---

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

---

What products have you designed which have entered high volume production?

1 Answers   Intel,

---

What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

---

Write a program to explain the comparator?

0 Answers  

---

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

---