Are you familiar with the term MESI?

0 Answers   Intel,

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Why do we use a Clock tree?

3 Answers   Intel,

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Explain the various MOSFET Capacitances & their significance?

1 Answers  

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How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

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What is the ideal input and output resistance of a current source?

0 Answers  

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Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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what is conductance and valence band?

1 Answers  

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

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Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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